The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to the retrieval and storage of multi-level data through a single input/output pin.
Modern electronic systems typically include a data storage device such as a dynamic random access memory (DRAM), static random access memory (SRAM) or other conventional memory device. The memory device stores data in vast arrays of memory cells. Each cell conventionally stores a single bit of data (a logical xe2x80x9c1xe2x80x9d or a logical xe2x80x9c0xe2x80x9d) and can be individually accessed or addressed. Data is output from a memory cell during a xe2x80x9creadxe2x80x9d operation, and data is stored into a memory cell during a xe2x80x9cwritexe2x80x9d operation.
In a standard read or write operation, a column decoder and a row decoder translate address signals into a single intersection of a row (wordline) and column (bitline) within the memory array. This function permits the memory cell at that location to be read from or for data to be placed into that cell. The processing of data is dependent on the time it takes to store or retrieve individual bits of data in the memory cells. Storing and retrieving the bits of data is controlled generally by a microprocessor, whereby data is passed to and from the memory array through a fixed number of input/output (I/O) lines and I/O pins. According to current digital circuit technology, each I/O pin can access, at most, one bit of data during an operation cycle. This substantially limits the potential bandwidth or speed of the memory device.
Modern applications call on electronic systems to process data at greater speeds. In order for the systems to accord these demands, the system components must increase their processing speeds. One method to increase the processing speeds is to provide additional I/O pins on the system components. However, space limitations on both microprocessor chips and memory chips preclude simply adding more and more I/O pins. Another method to increase processing speeds is to decrease the cycle time for retrieving and storing data. Upper limits for increasing cycle speeds are set by current feature size (F) of the discrete devices from which the integrated circuit is composed. Modern photolithographic techniques, however, limit the size of the circuits that can be formed from semiconductor and other materials. At some point, the lithography cannot create a fine enough image with sufficient clarity to decrease the size of the elements of the circuit any further.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, it is desirable to develop other methods to increase the data throughput or data bandwidth without requiring an increase in I/O pins or further decrease the cycle times.
The above mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A memory circuit and method of increasing the data bandwidth per cycle are described which do not require additional input/output pins or a decrease in access times.
In particular, an illustrative embodiment of the present invention includes a memory array. The memory array has multiple rows of wordlines and multiple columns of bitlines. The intersection of the multiple rows of wordlines and multiple columns of bitlines form multiple memory cells. There are a number of sense amplifiers coupled to the multiple columns of bitlines. A number of column decoders are coupled to the number of sense amps. Each column decoder can access a select number of bitlines simultaneously. There are a number of row decoders coupled to the multiple rows of wordlines. A number of input/output lines are coupled to the bitlines through the number of sense amplifiers. Also, a number of logic circuits are included which couple to a subset of the input/output lines. The logic circuits use multiple voltage levels or references to control the reading and writing to more than one memory cell simultaneously. The reading and writing operations pass multiple bits through a single input/output pin with each operation cycle.
In another embodiment, a memory circuit is provided which similarly has a memory array. The memory array has multiple rows of wordlines and multiple columns of bitlines. At the intersections of the multiple rows of wordlines and multiple columns of bitlines are located multiple memory cells. A number of sense amplifiers are coupled to the multiple columns of bitlines. A number of column decoders couple to the number of sense amps such that a column decoder selects the output of at least two (2) sense amps. A number of row decoders couple to the multiple rows of wordlines. There are a number of input/output lines coupled to the bitlines through the number of sense amplifiers. There are a number of logic circuits which have multiple inputs and outputs. Each of the logic circuits is coupled to a subset of the input/output lines. The outputs of at least one of the number of logic circuits individually couples to a number of pull-up or pull-down transistors. The inputs of at least one of the number of logic circuits individually couples to a number of comparators. Each of the office number of logic circuits uses multiple voltage levels to write to or read from more than one memory cell at a time.
In another embodiment, a method for writing to multiple memory cells using a single input pin is provided. The method includes receiving a voltage at the pin that represents values to be stored in several memory cells. The voltage at the pin is compared with a number of distinct voltage references using a number of comparators. The output of the comparing step is coupled to a logic circuit. The method includes the logic circuit outputting bits of data to a select number of input/output lines. A row in an array of memory cells is activated. The array has multiple rows of wordlines and multiple columns of bitlines. A select number of columns in the array of memory cells are activated simultaneously by a column decoder. The method further includes placing the bits of data located on the select number of input/output lines into memory cells located at the intersection of the activated row and select number of activated columns. The select number of input/output lines equals the select number of columns accessed simultaneously by one column decoder.
In another embodiment, a method for reading multiple memory cells using a single output pin is provided. The method includes activating a row in an array of memory cells. The array has multiple rows of wordlines and multiple columns of bitlines. The method also includes activating a select number of columns in the array of memory cells. The select number of columns are simultaneously accessed by a single column decoder. Bits of data located at the intersection of the activated row and select number of columns are placed onto a select number of input/output lines. The select number of input/output lines are then coupled to a logic circuit The logic circuit has a number of outputs and each output is individually coupled to a pull-up or a pull-down transistor. The method further includes coupling the pull-up and pull-down transistors to a single output pin.
In another embodiment, an information handling system is provided. The information handling system includes a central processing unit and a random access memory (RAM). The RAM has a number of input/output pins. The RAM has multiple rows of wordlines and multiple columns of bitlines. The RAM has a number of sense amplifiers coupled to the multiple columns of bitlines. The RAM has a column decoder coupled to the multiple columns of bitlines that accesses a select number of bitlines simultaneously. The RAM has a row decoder coupled to the multiple rows of wordlines. There are a number of input/output lines coupled to the number of bitlines through sense amplifiers. A number of first logic circuits are each coupled to a select number of input/output lines. There are a number of pull-up transistors and a pull-down transistor coupled between an input/output pin and the first logic circuit for reading data out of the random access memory. A number of comparators are coupled to each input/output pin and each comparator is connected to a distinct voltage reference. A second logic circuit is coupled to the number of comparators for an input/output pin. The second logic circuit couples to a select number of input/output lines at any one time for writing data into the random access memory. A system bus communicatively couples to the central processing unit and the RAM.
This invention enables an electronic system with a memory circuit to have a greater data bandwidth or speed without increasing the number of input/output pins or decreasing the access time of the part. It is advantageous over increasing the input/output pin count because it uses much less die area for the bond pad area and possibly less area for signal routing. The implementation of the present invention will enable memory circuits to operate faster without having to resize the transistors, change the memory addressing sequence, change the operating voltage, or using other methods for increasing the overall speed of microprocessors. This method of compressing data can be applied to any device that would benefit from the ability to transfer more data through a limited number of I/O pins.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.